Verilog- RTL Design Test
Verilog- RTL Design Test
Time:00:45:00
Est. Time: 00:45:00
Max Points: 58
Max Points: 58
This will submit your entire assessment.
Verilog- RTL Design Test
58
Max Points
All Problems (12)
TASKS
6 TasksPWM with 4-bit Resolution
Verilog•12 pts•Est: 11 min
Safe MUX
Verilog•6 pts•Est: 7 min
Nibble Swap
Verilog•4 pts•Est: 4 min
Half Adder using NAND Primitive
Verilog•6 pts•Est: 7 min
Guard Division by Zero
Verilog•6 pts•Est: 7 min
Universal Barrel Shifter
Verilog•12 pts•Est: 11 min
QUESTIONS
6 QuestionsOut-of-Bounds Bit
Verilog•2 pts•Est: 2 min
Unresolvable Contention
Verilog•2 pts•Est: 2 min
Case without default
Verilog•2 pts•Est: 2 min
Task - Step Up
Verilog•2 pts•Est: 2 min
Primitive - not
Verilog•2 pts•Est: 2 min
Shift Operator
Verilog•2 pts•Est: 2 min
Welcome To
Verilog- RTL Design Test
Test your Verilog design skills for VLSI and FPGA development. Ideal for engineers preparing for RTL and digital design job roles.
Duration
45min
Problems
12
Organization
Mock test
Sponsored By
Skills
Your assessment contains the following skills.
| Number | Skills | Problems |
|---|---|---|
| 1 | Verilog | 6 Tasks, 6 Questions |
Section 1
Verilog
6 Tasks, 6 Questions
Instructions
Read the instructions carefully before starting.
- This is a standard practice test; Your result will remain private.
- Please keep 45 minutes available and attempt the test without interruption.
- Tab switching is not allowed.
- Must use a laptop or desktop for attempting this test.
- Complete the test in one sitting.
- Use a stable internet connection and avoid refreshing or closing the page during the test.