83. Registers and Counters

A ring counter is a shift register whose last output is connected back to its first input.

Only one HIGH bit normally moves through the register.

3-Bit Architecture

For a 3-bit ring counter:

• D0 = Q2
• D1 = Q0
• D2 = Q1
• All flip-flops use a common clock.

Fig. 1: 3-bit Ring Counter

Working

Assume the initial state is 001.

At every active clock edge, the HIGH bit moves to the next position.

Table 1: Ring-Counter Sequence

A valid initial value must contain one HIGH bit. The state 000 cannot start the ring sequence by itself.

A Johnson counter is a shift register in which the inverted last output is connected back to the first input.

It is also called a:

• Twisted-ring counter
• Switch-tail ring counter

3-Bit Architecture

For a 3-bit Johnson counter:

• D0 = ~Q2
• D1 = Q0
• D2 = Q1
• All flip-flops use a common clock.

Fig. 2: 3-bit Johnsons Counter

Working

A 3-bit Johnson counter produces six different states.

Table 2: Johnson-Counter Sequence

For an n-bit Johnson counter:

Number of states = 2n

A ring counter needs an initial data pattern before shifting can begin.

Data can be loaded using:

• Synchronous loading
• Asynchronous loading

Synchronous Loading

In synchronous loading, data is loaded only at the active clock edge.

A 2-to-1 multiplexer is connected before every D input.

The control input LD selects between:

• LD = 1: Load parallel data
• LD = 0: Shift the stored data

Fig. 3: Ring Counter with Synchronous Data Loading

Connections

For parallel data P2P1P0:

D0 = LD · P0 + ~LD · Q2
D1 = LD · P1 + ~LD · Q0
D2 = LD · P2 + ~LD · Q1

Table 3: Synchronous Loading Operation

Working

• Apply the required data to P2P1P0.
• Set LD = 1.
• Give one active clock edge to load the data.
• Set LD = 0.
• Further clock edges shift the loaded data in a ring.

Asynchronous Loading

Asynchronous loading uses active-LOW PRESET and CLEAR inputs.

The data is loaded without waiting for a clock edge.

Table 4: Asynchronous Bit Loading

Fig. 4: Ring Counter with Asynchronous Data Loading

Working

To load 101:

• For Q2 = 1: ~PRE2 = 0, ~CLR2 = 1
• For Q1 = 0: ~PRE1 = 1, ~CLR1 = 0
• For Q0 = 1: ~PRE0 = 0, ~CLR0 = 1

After loading:

• Set all ~PRE = 1
• Set all ~CLR = 1
• Apply the clock to begin shifting

A controlled counter can work as either a ring counter or a Johnson counter.

A control input C selects the feedback signal.

3-Bit Connections

P0 = Q2 ⊕ C
P1 = Q0
P2 = Q1

Fig. 5: Ring/Johnsons Counter with Control Input C

Table 5: Counter Selection

Data Loading

A 3-bit parallel data input can be used to set the initial state.

• Ring mode requires a one-HIGH pattern such as 001.
• Johnson mode can begin from 000.

Working

When C = 0

The XOR output follows Q2.

D0 = Q2

The stored bit pattern circulates through the three stages.

When C = 1

The XOR output becomes ~Q2.

D0 = ~Q2

The circuit follows the Johnson-counter sequence.

Registers and counters can be combined to store data, count clock cycles and control circuit operation.

Clock-Gating Circuit

The clock-gating circuit produces a fixed number of output clock edges.

Inputs and Output

Inputs:

• SEND
• 3-bit CYCLES
• Clock

Output:

• CLK_OUT

Fig. 6: Programmable Clock Gating Circuit

Main Blocks

The circuit contains:

• Active-HIGH output falling-edge detector
• Negative-edge-triggered JK flip-flop
• 3-bit load/count down counter
• Zero-detection circuit
• AND clock gate

Edge Detection

When SEND changes from 1 → 0, the edge detector produces one pulse:

SEND_EDGE = 1

This pulse is connected to the J input of the JK flip-flop.

Counter Control

The counter uses:

• LD = 1: Load CYCLES
• LD = 0: Count down

The connection is:

LD = ~ENABLE

Therefore:

• ENABLE = 0: Load mode
• ENABLE = 1: Count mode

Stop Detection

The counter reaches zero when:

Q2Q1Q0 = 000

The STOP equation is:

STOP = ~(Q0 + Q1 + Q2)

STOP is connected to the K input of the JK flip-flop.

Clock Output

CLK_OUT = ENABLE · Clock

Working

1. During idle mode, ENABLE = 0.
2. The counter loads the value available at CYCLES.
3. When SEND changes from HIGH to LOW, SEND_EDGE = 1.
4. The JK flip-flop sets and makes ENABLE = 1.
5. LD becomes 0, so the counter starts counting down.
6. The input clock passes through the AND gate.
7. When the counter reaches 000, STOP = 1.
8. The JK flip-flop resets and makes ENABLE = 0.
9. The clock gate closes.

Table 6: Clock-Gating Operation

The number of output clock edges is controlled by the value stored in CYCLES.

Digital Dice

The digital dice combines:

• A high-speed MOD-6 counter
• A 3-bit PIPO register
• A rising-edge detector
• A 7-segment BCD display

Fig. 7: Digital Dice

Counter Operation

The MOD-6 counter repeatedly counts:

1 → 2 → 3 → 4 → 5 → 6 → 1

The counter runs continuously using a high-speed clock.

Roll Input

The push button R produces HIGH when pressed.

An active-HIGH output rising-edge detector generates one pulse when:

R: 0 → 1

The edge-detector output is connected to the clock of the PIPO register.

Working

1. The MOD-6 counter changes rapidly from 1 to 6.
2. The user presses R.
3. The rising-edge detector generates one pulse.
4. The PIPO register stores the current counter value.
5. The stored value appears on the 7_Seg_BCD_display.
6. The display keeps the value until the next button press.

The captured value appears random because the counter changes faster than the user can observe.

Target Landing Game

The target landing game uses an 11-bit ring counter connected to 11 active-HIGH LEDs.

LED Sequence

White → White → Blue → Blue → Red → Yellow → Red → Blue → Blue → White → White

The illuminated LED shows the landing position and score category.

Inputs:

• P – Point button
• R – Reset/Run button
• POWER – Forces reset mode

Fig. 8: Target Landing Game Circuit

Reset and Run Control

Button R uses an active-HIGH output rising-edge detector.

Its output R_EDGE clocks a T flip-flop.

Connections:

• T = 1
• PRE = 1
• Output Q = RST_N

Each press of R toggles RST_N.

Table 7: Reset and Run Modes

POWER keeps the circuit in reset mode regardless of the button inputs.

Starting the Ring

Another active-HIGH output rising-edge detector monitors RST_N.

When RST_N changes from 0 → 1:

RST_EDGE = 1

The first ring-register input is:

D0 = RST_EDGE + Q10

Therefore:

• RST_EDGE inserts the first HIGH bit.
• Q10 provides normal ring feedback.

The HIGH bit then moves rapidly through the LEDs.

Stopping the LED

Button P uses another active-HIGH output rising-edge detector.

Its output P_EDGE clocks a D flip-flop.

Connections:

• D = 1
• Clock = P_EDGE
• Q = OF
• ~Q controls the ring-counter clock gate

The gated ring clock can be represented as:

CLK_RING = Clock · RST_N · ~OF

Working

1. In reset mode, all LEDs remain OFF.
2. Press R to change RST_N from 0 to 1.
3. RST_EDGE inserts one HIGH bit into the ring counter.
4. The HIGH bit moves rapidly through the LEDs.
5. Press P to generate P_EDGE.
6. The D flip-flop stores OF = 1.
7. ~OF becomes 0 and blocks the ring clock.
8. The currently selected LED remains ON.
9. Pressing P again does not restart the circuit.
10. Press R to return to reset mode.
11. Press R again to start a new round.

Custom UART Frame

The custom UART circuit sends a 4-bit data word with one start bit and one stop bit.

The complete frame contains six bits:

Start Bit + 4 Data Bits + Stop Bit

The transmitter uses a PISO register, and the receiver uses a SIPO register.

Fig. 9: Custom UART Model

Main Inputs and Outputs

Inputs:

• 6-bit parallel data (Input_Data)
• SEND
• Clock
• ~RESET

Outputs:

• Received 6-bit frame (D_Out)
• TX

Start Detection

An active-HIGH output falling-edge detector monitors SEND.

When:

SEND: 1 → 0

It produces:

SEND_P = 1

SEND_P is connected to the J input of a positive-edge-triggered JK flip-flop.

Transmission Control

The JK flip-flop output is:

ENABLE = Q

The transmission flag is:

TX = ENABLE

The gated shift clock is:

SHIFT_CLK = ENABLE · Clock

Bit Counter

A 3-bit synchronous up counter counts the transmitted bits.

The counter counts from 0 to 5.

The STOP output becomes HIGH at decimal 5:

STOP = Q2 · ~Q1 · Q0

STOP is connected to the K input of the JK flip-flop.

The counter reset control uses:

~CLR = ENABLE

Therefore:

• ENABLE = 0: Counter remains reset.
• ENABLE = 1: Counter operates normally.

Working

1. ~RESET = 0 resets the complete circuit.
2. The 4-bit data, start bit and stop bit are loaded into the PISO register.
3. SEND changes from HIGH to LOW.
4. The falling-edge detector generates SEND_P.
5. The JK flip-flop sets ENABLE = 1.
6. TX becomes HIGH.
7. The gated clock shifts one bit from the PISO register during each clock cycle.
8. The SIPO register receives the bits from the serial line.
9. The synchronous counter counts the six transmitted bits.
10. When the count reaches 5, STOP = 1.
11. The JK flip-flop resets and makes ENABLE = 0.
12. The shift clock stops.
13. TX returns LOW.
14. The received 6-bit frame remains stored in the SIPO register.

Table 8: UART Transmission Stages

The circuit transmits exactly one 6-bit frame for each valid SEND falling edge.