Question.1
How would you use the Verilog replication operator to sign-extend val (with val[3] representing the sign) into the 8-bit extended bus?
val
val[3]
extended
wire [3:0] val; wire [7:0] extended; // Which assigns `extended` correctly?
Select Answer
assign extended = {val[3], val[3], val[3], val[3], val};
assign extended = {4{val[3]}, val[3:0]};
assign extended = { {4{val[3]}}, val };
assign extended = {val, 4'b0000};
