44. Bus Error Checker

How do you plan to solve it?

this problem help me for understand the and , or logic gates when X be happen get z.  instead of this xor and xnor gates as used for check whether x don't care condition there or not.

/*Write your code here*/
module error_checker_xz(input [7:0]bus,output all_known,has_unknown,output [7:0]bus_if_known);
wire c = (^bus === 1'bx);
assign all_known = c ? 1'b0:1'b1;
assign has_unknown = c ? 1'b1:1'b0;
assign bus_if_known = c ? 8'h00:bus;
endmodule