Verilog

Wire

Fan-Out Wire

Multiple Drivers

NOT Gate

OR Gate

AND Gate

XOR Gate

4-to-1 Multiplexer by Module Instantiation

XOR Gate Using Basic Gates

Splitting Vector

Vector Concatenation

Vector Bitwise Operators

Parity Checker

Logical Shifter

Elevator Indicator

Parking Lot Status

Binary to Gray Code Converter

Battery LED Bar

Modules

Number Representation

Vectors - I

Vectors - II

Open-Drain I2C SDA line

Open-Source Line using tri0

Single-Driver Data Line using uwire

Shared Line using wor

LED Toggle on Rising Edge

Divide-by-4 Tick Generator

One Shot Pulse

PWM with 4-bit Resolution

Parameterized LED Blinker

Board-Clock Configuration using Parameter Pass-Through

Data Types

Procedural Constructs

AND Primitive

4-Input NAND Gate Primitive

Tri-State Buffer

Multiplexer Using Primitives

Half Adder using NAND Primitive

Primitives

Assignment - Blocking vs Non-Blocking

Equality Operators

Guard Division by Zero

Bus Error Checker

Signed vs Unsigned Compare

Operators - I

Operators - II

Safe MUX

Brake Light Control

3-Way Selector

Opcode Decoder

Instruction Decoder with Don’t-Care

8-to-3 Priority Encoder

Population Count

MUX Tree using Loops

Control Flow Basics

Using Functions

Maximum of Two Numbers

Absolute Value

Using Task

Vector Min/Max Pair

Nibble Swap

Functions and Tasks Basics

Full Adder

Ripple Carry Adder

Demultiplexer

Decoder

4-bit Comparator

Binary Subtractor

Universal Barrel Shifter

Arithmetic Logic Unit

7-Segment Display Decoder

SR Latch

Gated SR Latch

D Latch

D Latch with Enable-Synchronous Reset

D Flip-Flop

D Flip-Flop with Asynchronous Reset

DFF with Synchronous Reset

DFF with Async Reset and Preset

JK Flip-Flop

JK Flip-Flop with Enable

T Flip-Flop

T Flip-Flop with Asynchronous Preset and Reset

4-bit Register

4-bit Register with Synchronous Reset

4-bit Bidirectional Shift Register

Parallel-In Serial-Out Register

Serial-In Parallel-Out Register