44. Bus Error Checker

How do you plan to solve it?

module error_checker_xz(input[7:0] bus,
                        output all_known,
                        output has_unknown,
                        output[7:0] bus_if_known);

        wire[7:0] result1;
        wire[7:0] result2;

genvar i;
generate begin:gen
    for( i=0; i<=7; i=i+1)begin
       assign result1[i] = (bus[i] === 1'b1 || bus[i] === 1'b0);
       assign result2[i] = (bus[i] === 1'b1 || bus[i] === 1'b0);

    end
end
endgenerate

    assign all_known = &result1;
    assign has_unknown = ~(&result2);
    assign bus_if_known = (&result1) ? bus : 0;





endmodule