28. Divide-by-4 Tick Generator

How do you plan to solve it?

module tick_div4(
    input  wire clk,
    input  wire rst,
    output reg  tick
);

    reg [1:0] count;

    always @(posedge clk) begin
        if (rst) begin
            count <= 2'b00;
            tick  <= 1'b0;
        end else begin
            if (count == 2'b11) begin
                count <= 2'b00;
                tick  <= 1'b1;   // 1-cycle pulse
            end else begin
                count <= count + 1'b1;
                tick  <= 1'b0;
            end
        end
    end

endmodule