28. Divide-by-4 Tick Generator

How do you plan to solve it?

module tick_div4 (
  input wire clk, rst,
  output reg tick
);
  reg [1:0] cnt;
  always @(posedge clk) begin 
    if (rst) begin 
      cnt <= 0;
      tick <= 0;
    end else begin 
      if (cnt == 3) begin 
        cnt <= 0;
        tick <=1;
      end else begin 
        cnt <= cnt + 1;
        tick <= 0;
      end
    end
  end
endmodule

/*
module tick_div4 (
  input wire clk, rst,
  output reg tick
);
  reg [1:0] cnt;