28. Divide-by-4 Tick Generator

How do you plan to solve it?

module tick_div4(
  input  wire clk,
  input  wire rst,
  output reg  tick
);
  reg [1:0] cnt;
  reg [1:0]count;
  reg [1:0]count_next;
  always @(*) begin
        // default values
        count_next = count;
        
        // increment and wrap every 4 cycles
        if (count == 2'b11)
            count_next = 2'b00;
        else
            count_next = count + 1;
    end

    // -------------------------------
    // State and output update (sequential)
    // -------------------------------
    always @(posedge clk) begin
        if (rst) begin
            count <= 2'b00;
            tick  <= 1'b0;             // reset realigns, pulse occurs after 4 clocks
        end
        else begin
            count <= count_next;

            // tick pulse when counter wraps from 3 → 0
            tick <= (count == 2'b11);
        end
    end
endmodule