28. Divide-by-4 Tick Generator

How do you plan to solve it?

module tick_div4(
  input  wire clk,
  input  wire rst,
  output reg  tick
);
  reg [1:0] cnt=2'b00;
  always @(posedge clk) begin
    // Write your code here
   if (rst==1'b0)begin
    
    if (cnt == 2'b11) begin
    tick <= 1'b1;
    cnt<=2'b00;
    end
    else begin
    tick <= 1'b0;
    cnt <= cnt+2'b01;   
    end end
  end
endmodule