28. Divide-by-4 Tick Generator

How do you plan to solve it?

module tick_div4(
  input  wire clk,
  input  wire rst,
  output reg  tick
);
  reg [1:0] cnt;
  always @(posedge clk) begin
    if(rst)
    cnt <= 1'b0;
    else
    cnt <= cnt +1; 

    if(cnt == 2'b11)
    tick <= 1'b1;
    else
    tick <= 1'b0;   
  end


endmodule