28. Divide-by-4 Tick Generator

First, for a better code readability and debugging, I use and recommend using "if else" statement on rst. 

Second, it would be safer to add another conditional statement putting cnt at 0. But in this case, since it is a clk division by 4 and cnt is coded on 2 bits, it will just go back to 0 if we add 1 when cnt = 3.

module tick_div4(
  input  wire clk,
  input  wire rst,
  output reg  tick
);
  reg [1:0] cnt;
  always @(posedge clk) begin
    if (rst) begin
      cnt <= 2'd0;
      tick <= 1'b0;
    end else begin
      cnt <= cnt + 2'd1;
      tick <= (cnt == 2'd3) ? 1'b1 : 1'b0;
    end
  end
endmodule