module tick_div4(
input wire clk,
input wire rst,
output reg tick
);
reg [1:0] cnt;
always @(posedge clk) begin
if(rst)begin
cnt <=2'b0;
tick<=0;end
else if (cnt == 2'b11 )begin
tick<=1;
cnt<=0;end
else begin
cnt<=cnt+1;
tick <=0;
end
// Write your code here
end
endmodule