module tick_div4(
input wire clk,
input wire rst,
output reg tick
);
reg [1:0] cnt;
always @(posedge clk)
begin
if(rst)
begin
cnt<=2'b00;
tick<=1'b0;
end
else
begin
cnt<=cnt+1;
if(cnt==2'b11)
tick<=1'b1;
else
tick=1'b0;
end
// Write your code here
end
endmodule