module tick_div4(
input wire clk,
input wire rst,
output reg tick
);
reg [1:0] cnt;
always @(posedge clk) begin
// Write your code here
if(rst)begin
// tick <= (cnt == 3);
tick <= 0;
cnt <= 0;
end
else begin
tick <= (cnt == 3);
cnt <= cnt + 1;
end
end
endmodule