28. Divide-by-4 Tick Generator

How do you plan to solve it?

module tick_div4(
  input  wire clk,
  input  wire rst,
  output reg  tick
);
  reg [1:0]cnt;
  always@(posedge clk) begin
    if (rst) begin
    tick<=1'b0;
    cnt<=2'b0; end
    else if (cnt==2'd3) begin
    tick<=1'b1;
    cnt<=2'b0; end
    else begin
    cnt<=cnt+1;
    tick<=1'b0; end
  end
endmodule