28. Divide-by-4 Tick Generator

How do you plan to solve it?

module tick_div4(
  input  wire clk,
  input  wire rst,
  output reg  tick
);
  reg [1:0] cnt;
  always @(posedge clk) begin
    if(rst) begin
      cnt <= 2'b00;
      tick <= 0;
    end
    else begin
      cnt <= cnt + 1;
      if(cnt == 2'b11) begin
        tick <= 1;
        cnt <= 2'b00;
      end
      else begin
        tick <= 0;
      end
    end    
  end
endmodule