module tick_div4(
input wire clk,
input wire rst,
output reg tick
);
reg [1:0] cnt;
always @(posedge clk) begin
// Write your code here
if(rst) begin
//rst <= 0;
tick <= 1'b0;
cnt <= 2'b0;
end
else begin
cnt <= cnt + 2'd1;
if(cnt == 2'b11) tick <= 1'b1;
else tick <= 1'b0;
end
end
endmodule