module tick_div4(
input wire clk,
input wire rst,
output reg tick
);
reg [1:0] cnt;
always @(posedge clk) begin
// Write your code here
tick<=0;
if(rst) begin
tick<=0;
cnt<=0;
end
else if(cnt==2'd3) begin
tick<=1;
cnt<=0;
end
else cnt<=cnt+1'b1;
end
endmodule