28. Divide-by-4 Tick Generator

How do you plan to solve it?

module tick_div4(
  input  wire clk,
  input  wire rst,
  output reg  tick
);
  reg [1:0] cnt;
  always @(posedge clk) 
    begin
      cnt<=cnt+1;
      if(cnt==2'd3)
        begin
          tick <= 1'b1;
          cnt <= 2'd0;
        end
      else if(rst==1)
        begin
          tick <= 1'b0;
          cnt <= 2'd0;
        end
      else 
        tick <= 1'b0;
    end
endmodule