28. Divide-by-4 Tick Generator

How do you plan to solve it?

module tick_div4(
  input  wire clk,
  input  wire rst,
  output reg  tick
);
  reg [1:0] cnt;

  always @(posedge clk) 
  begin
      
      if(rst)
      begin
         tick = 0;
         cnt = 0;
      end 

      else if(cnt==3)
      begin
         tick = 1;
         cnt = 0;
      end 
      
      else 
      begin
         tick = 0;
         cnt = cnt +1;
      end
    
  end
endmodule