28. Divide-by-4 Tick Generator

How do you plan to solve it?

// Module: tick_div4
// Purpose: Generate a one-clock-wide pulse every 4th rising edge of clk

module tick_div4 (
    input  wire clk,
    input  wire rst,
    output reg  tick
);

  // 2-bit counter to count 0–3
  reg [1:0] count;

  // Synchronous reset and tick generation
  always @(posedge clk) begin
    if (rst) begin
      count <= 2'b00;
      tick  <= 1'b0;
    end
    else begin
      if (count == 2'b11) begin
        count <= 2'b00;
        tick  <= 1'b1;  // Generate 1-cycle tick
      end
      else begin
        count <= count + 1'b1;
        tick  <= 1'b0;
      end
    end
  end

endmodule