28. Divide-by-4 Tick Generator

How do you plan to solve it?

module tick_div4(
  input  wire clk,
  input  wire rst,
  output reg  tick
);
  reg [1:0] cnt;
  always @(posedge clk)
   begin
    tick<=rst? 1'b0 : (cnt==2'd3);
    cnt<=rst?2'b0: cnt+2'd1;
  end
endmodule