28. Divide-by-4 Tick Generator

How do you plan to solve it?

module tick_div4(
  input  wire clk,
  input  wire rst,
  output reg  tick
);
  reg [1:0] cnt;
  always @(posedge clk) begin
    // Write your code here
    if(rst) begin
      cnt <= 2'd 0;
      tick <= 1'b 0;
    end
    else begin
      cnt <= cnt + 1;
      tick <= &cnt;
    end
  end
endmodule