28. Divide-by-4 Tick Generator

How do you plan to solve it?

module tick_div4(
  input  wire clk,
  input  wire rst,
  output reg  tick
);
  reg [1:0] cnt;
  always @(posedge clk or posedge rst) begin
    if (rst) cnt <= 0;
    else cnt <= cnt + 1;

    if (cnt | rst) tick <= 0;
    else tick <= 1;
  end
endmodule