28. Divide-by-4 Tick Generator

How do you plan to solve it?

module tick_div4(
  input  wire clk,
  input  wire rst,
  output reg  tick
);
  reg [1:0] cnt;
  always @(posedge clk) begin
    if (rst)
      cnt <= 2'b00;
    else
      cnt <= cnt + 1;
  end

  always @(posedge clk) begin
    if (rst)
      tick <= 2'b00;
    else
      tick <= (cnt == 2'd3);
  end
endmodule