module tick_div4(
input wire clk,
input wire rst,
output reg tick
);
reg [1:0] cnt;
always @(posedge clk) begin
// Write your code here
if(rst == 1) begin
cnt <= 0;
end
else begin
cnt <= cnt + 1;
end
if(cnt == 3) begin
tick <= 1;
cnt <= 0;
end
else begin
tick <= 0;
end
end
endmodule