28. Divide-by-4 Tick Generator

How do you plan to solve it?

`timescale 1ns / 1ps

module tick_div4(
    input  wire clk,
    input  wire rst,
    output reg  tick
);
    reg [1:0] cnt;

    always @(posedge clk) begin
        if (rst) begin
            cnt  <= 0;
            tick <= 0;
        end else begin
            cnt  <= cnt + 1;
            tick <= (cnt == 2'b11);
        end
    end
endmodule