28. Divide-by-4 Tick Generator

module tick_div4(
  input  wire clk,
  input  wire rst,
  output reg  tick
);
  reg [1:0] cnt;
  always @(posedge clk) begin
    // Write your code here
    tick <= rst ? 1'b0:(cnt == 2'b11);
    cnt <= rst ? 1'b0:(cnt + 2'b01);
    
  end
endmodule

module tick_div4(
  input  wire clk,
  input  wire rst,   
  output reg  tick
);

  reg [1:0] cnt;

  always @(posedge clk) begin
    if (rst) begin
      cnt  <= 2'b00;
      tick <= 1'b0;
    end else begin
      if (cnt == 2'b11) begin
        cnt  <= 2'b00;
        tick <= 1'b1;  
      end else begin
        cnt  <= cnt + 1'b1;
        tick <= 1'b0;
      end
    end
  end

endmodule