module tick_div4(
input wire clk,
input wire rst,
output reg tick
);
reg [1:0] cnt;
always @(posedge clk) begin
// Write your code here
if(rst) begin
tick<=0;
cnt<=0;
end
else begin
if(cnt == 2'b11) begin
tick <=1;
cnt <=0;
end
else begin
tick <=0;
cnt= cnt+1;
end
end
end
endmodule