28. Divide-by-4 Tick Generator

How do you plan to solve it?

//tick synchronous
module tick_div4(
    input  wire clk,
    input  wire rst,
    output reg  tick
);  
    //counting cycle
    reg [1:0] cnt;

  always @(posedge clk ) begin
    if (rst) begin
        cnt <= 2'b00; //reset and starting to count
        tick <= 1'b0; //reset
    end
    else begin
    if (cnt == 2'b11) begin
        cnt <= 2'b00;  //reset counter
        tick <= 1'b1;  //tick 
    end
    else begin
        //in default, increase counter and tick equal to 0
        cnt <= cnt + 1'b1;
        tick <= 1'b0;
    end 
    end 
  end
endmodule