module tick_div4(
input wire clk,
input wire rst,
output reg tick
);
reg [1:0] cnt;
always @(posedge clk) begin
if(rst)begin
tick=1'b0;
cnt=1'b0;
end else begin
if(cnt==2'd3)begin
cnt=1'b0;
tick=1'b1;
end else begin
cnt=cnt+1;
tick=1'b0;
end
end
end
endmodule