28. Divide-by-4 Tick Generator

How do you plan to solve it?

module tick_div4 (
    input  wire clk,
    input  wire rst,    // synchronous, active-high reset
    output reg  tick
);

reg [1:0] count;  // counts 0 to 3

always @(posedge clk) begin
    if (rst) begin
        count <= 2'd0;
        tick  <= 1'b0;
    end else begin
        if (count == 2'd3) begin
            count <= 2'd0;
            tick  <= 1'b1;   // generate 1-cycle pulse
        end else begin
            count <= count + 2'd1;
            tick  <= 1'b0;
        end
    end
end

endmodule