module safe_div8(
input wire [7:0] dividend,
input wire [7:0] divisor,
output wire [7:0] q,
output wire [7:0] r,
output wire div_by_zero
);
assign div_by_zero = (divisor == 8'd0);
assign q = div_by_zero ? 8'd0 : (dividend / divisor);
assign r = div_by_zero ? 8'd0 : (dividend % divisor);
endmodule