module safe_div8 (
input [7:0] dividend,
input [7:0] divisor,
output [7:0] q,
output [7:0] r,
output div_by_zero
);
assign div_by_zero = (divisor == 8'b0);
assign q = (div_by_zero) ? (8'b0) : (dividend/divisor);
assign r = (div_by_zero) ? (8'b0) : (dividend % divisor);
// TODO: implement with ternary (?:)
endmodule