module safe_div8 (
input [7:0] dividend,
input [7:0] divisor,
output [7:0] q,
output [7:0] r,
output div_by_zero
);
wire a = |divisor;
wire [7:0] safe_divisor = a ? divisor : 8'd1; // Ngăn chia cho 0 nội bộ
assign q = a ? (dividend / safe_divisor) : 8'd0;
assign r = a ? (dividend % safe_divisor) : 8'd0;
assign div_by_zero = ~a;
endmodule