module safe_div8 (
input [7:0] dividend,
input [7:0] divisor,
output wire [7:0] q,
output wire [7:0] r,
output wire div_by_zero
);
assign div_by_zero=(divisor==8'd0)?1'b1:1'b0;
assign q=(div_by_zero==0)?(dividend / divisor):8'd0;
assign r=(div_by_zero==0)?(dividend % divisor):8'd0;
endmodule