How do you plan to solve it?
/*Write your code here*/ module pwm4_basic ( input wire clk, input wire rst, input [3:0] duty, output reg pwm_out ); reg [3:0] cnt; always @(posedge clk) begin pwm_out <= rst ? 0 : (cnt < duty); cnt <= rst ? 4'b0000 : (cnt + 4'b0001); end endmodule