30. PWM with 4-bit Resolution

How do you plan to solve it?

module pwm4_basic (
    input        clk,
    input        rst,
    input  [3:0] duty,
    output reg   pwm_out
);

    reg [3:0] cnt;

    always @(posedge clk) begin
        if (rst) begin
            cnt      <= 4'd0;
            pwm_out  <= 1'b0;
        end else begin
            cnt <= cnt + 4'd1;
            if (cnt < duty)
                pwm_out <= 1'b1;
            else
                pwm_out <= 1'b0;
        end
    end
endmodule