30. PWM with 4-bit Resolution

How do you plan to solve it?

/*Write your code here*/
module pwm4_basic(
    input clk,
    input rst,
    input wire [3:0] duty,
    output reg pwm_out
);
reg[3:0] count;

always@(posedge clk) begin
count <= rst?1'b0:(count+4'b0001);
pwm_out <= rst?1'b0:(count<duty);
end


endmodule