30. PWM with 4-bit Resolution

How do you plan to solve it?

module pwm4_basic (
    input  wire       clk,
    input  wire       rst,
    input  wire [3:0] duty,
    output reg        pwm_out
);

    reg [3:0] counter;

    always @(posedge clk) begin
        if (rst) begin
            // Synchronous reset: Realignment
            counter <= 4'd0;
            pwm_out <= 1'b0;
        end
        else begin
            // Internal counter increments every clock (0 to 15)
            counter <= counter + 1'b1;

            // PWM logic: High for 'duty' clocks in every 16
            if (counter < duty) begin
                pwm_out <= 1'b1;
            end
            else begin
                pwm_out <= 1'b0;
            end
        end
    end

endmodule