30. PWM with 4-bit Resolution

Assumption : duty will change only after 16 cycles else it will lead to a unexpected output behaviour

/*Write your code here*/
module pwm4_basic(
    input clk,rst,
    input [3:0] duty,
    output reg pwm_out
);

reg [3:0] cnt;

always @(posedge clk)begin
    if(rst) begin
        cnt <= 0;
        pwm_out <= 1'b0;
    end
    else begin
        pwm_out <= (cnt < duty);
        cnt <= cnt + 1;
    end
end

endmodule