30. PWM with 4-bit Resolution

module pwm4_basic (
    input clk,
    input rst,
    input [3:0] duty,
    output reg pwm_out
);
    reg [3:0] counter;

    always @(posedge clk) begin
        if (rst) begin
            counter <= 4'h0;
            pwm_out <= 1'b0;
        end else begin
            counter <= counter + 1;
            pwm_out <= (counter < duty) ? 1'b1 : 1'b0;
        end
    end
endmodule