30. PWM with 4-bit Resolution

How do you plan to solve it?

module pwm4_basic(
    input wire clk,
    input wire rst,
    input [3:0]duty,
    output reg pwm_out
);
reg [3:0]cnt;
always@(posedge clk)
begin
    if(rst)
    begin
    cnt<=1'b0;
    pwm_out=1'b0;
    end
    else
    begin
       cnt     <= cnt + 1'b1;
    pwm_out <= (cnt < duty);
    end
end
endmodule