/*Write your code here*/
module pwm4_basic (
input clk,
input rst,
input [3:0] duty,
output reg pwm_out
);
reg [3:0] cnt = 4'h0;
//inital cnt = 4'h0;
always @(posedge clk) begin
pwm_out <= rst ? 1'b0 : (cnt < duty);
cnt <= (rst) ? 4'h0 : (cnt + 1'b1);
end
endmodule