30. PWM with 4-bit Resolution

How do you plan to solve it?

module pwm4_basic(
    input clk,
    input rst,
    input [3:0] duty,
    output reg pwm_out
);

reg [3:0] counter;

always @(posedge clk) begin
    if (rst)
        counter <= 4'd0;
    else
        counter <= counter + 1;
end

always @(posedge clk) begin
    if (rst)
        pwm_out <= 1'b0;
    else
        pwm_out <= (counter < duty);
end

endmodule