30. PWM with 4-bit Resolution

How do you plan to solve it?

module pwm4_basic(
    input clk,rst,
    input [3:0]duty,
    output reg pwm_out
);
    reg [3:0] cnt;
    always@(posedge clk) begin
        if(rst) begin
            cnt<=0;
            pwm_out<=0;
        end
        else begin
      cnt <= cnt + 1'b1;               
      pwm_out <= (cnt < duty) ? 1'b1 : 1'b0; 
    end
  end
endmodule