30. PWM with 4-bit Resolution

How do you plan to solve it?

module pwm4_basic(
    input clk,
    input rst,
    input [3:0] duty,
    output reg pwm_out
);
reg [3:0] cnt;
always @(posedge clk) begin
    if(rst) begin
        pwm_out <= 1'b0;
        cnt <= 1'b0;
    end
    else begin 
        cnt <= cnt + 4'd1;
    end

    pwm_out <= (cnt < duty);
end
endmodule