30. PWM with 4-bit Resolution

How do you plan to solve it?

// Module: pwm4_basic
// Purpose: Generate a PWM signal with 4-bit resolution (0–15 duty cycle)

module pwm4_basic (
    input  wire       clk,      // system clock
    input  wire       rst,      // synchronous active-high reset
    input  wire [3:0] duty,     // duty cycle (0–15)
    output reg        pwm_out   // PWM output
);

  // 4-bit counter for 16-clock PWM frame
  reg [3:0] counter;

  // Synchronous logic: counter and PWM generation
  always @(posedge clk) begin
    if (rst) begin
      counter <= 4'b0000;      // reset counter
      pwm_out <= 1'b0;         // output low during reset
    end
    else begin
      counter <= counter + 1'b1;               // increment counter every clock
      pwm_out <= (counter < duty) ? 1'b1 : 1'b0; // compare counter to duty
    end
  end

endmodule