How do you plan to solve it?
/*Write your code here*/ module pwm4_basic(clk,rst,duty,pwm_out); input clk,rst; input [3:0]duty; output reg pwm_out; reg[3:0]cnt; always@(posedge clk) begin pwm_out<=rst?1'b0:(cnt<duty); cnt<=rst?4'd0:(cnt+4'd1); end endmodule